Intelligent memory systems(智能存储系统)

This book presents the thoroughly refereed post-proceedings of the Second International Workshop on Intelligent Memory Systems, IMS 2000, held in Cambridge, MA, USA, in November 2000.The nine revised full papers and six poster papers presented were carefully reviewed and selected from 28 submissions. The papers cover a wide range of topics in intelligent memory computing; they are organized in topical sections on memory technology, processor and memory architecture, applications and operating systems, and compiler technology.

Memory Technology
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
　Software Controlled Reconfigurable On-Chip Memory　for High Performance Computing
Processor and Memory Architecture
　Content-Based Prefetching: Initial Resul
　Memory System Support for Dynamic Cache Line Assembly
　Adaptively Mapping Code in an Intelligent Memory Architecture
Applications and Operating Systems
　The Characterization of Date Intensive Memory Workloads　on Distributed PIM Systems
　Memory Management in a PIM-Based Architecture
Compiler Technology
　Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
　FlexCache: A Framework for Flexible Compiler Generated Data Caching
Poster Session
　Aggressive Memory-Aware Compilation
　Energy/Performance Design of Memory Hierarchies　for Processor-in-Memory Chips
　SAGE: A New Analysis and Optimization System for FlexRAM Architecture
　Performance/Energy Efficiency of Variable Line-Size Caches　for Intelligent Memory Systems
　The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
　Compiler-Directed Cache Line Size Adaptivity
Workshop Notes
Author Index