Integrated Circuit and System Design(集成电路与系统设计：功率与定时建模、优化和模拟/会议录)

This book constitutes the refereed proceedings of the 14th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2004, held in Santorini, Greece in September 2004.
The 85 revised papers presented together with abstracts of 6 invited presentations were carefully reviewed and selected from 152 papers submitted. The papers are organized in topical sections on buses and communication, circuits and devices, low power issues, architectures, asynchronous circuits, systems design, interconnect and physical design, security and safety, low-power processing, digital design, and modeling and simulation.

Keynote Speech
Connecting E-Dreams to Deep-Submicron Realities
Invited Talks
Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization
Low-Voltage Embedded RAMs - Current Status and Future Trends
Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing
Embedded Tutorials
Leakage in CMOS Circuits - An Introduction
The Certainty of Uncertainty: Randomness in Nanometer Design.
Session 1: Buses and Communication
Crosstalk Cancellation for Realistic PCB Buses
A Low-Power Encoding Scheme for GigaByte Video Interfaces
Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures
Perfect 3-Limited-Weight Code for Low Power I/O
A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses
Session 2: Circuits and Devices (I)
Performance Metric Based Optimization Protocol
Temperature Dependence in Low Power CMOS UDSM Process
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques
High Yield Standard Cell Libraries: Optimizatibfi and Modeling
A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits
Session 3: Low Power (I)
Sleepy Stack Reduction of Leakage Power
A Cycle-Accurate Energy Estimator for CMOS Digital Circuits
Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures
Reducing Cross-Talk Induced Power Consumption and Delay
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates,
Session 4: Architectures
Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS
……
Session 5: Asynchronous Circuits
Session 6: System Design
Session 7: Circuits and Devices(II)
Session 8: Interconnect and Physical Design
Session 9: Security and Safety
Session 10: Low Power(II)
Session 11: Low-Power Processing (Poster)
Session 12: Digital Design(Poster)
Session 13：Modeling and Simulation(Poster)
Author Index