Computer Aided Verification （计算机辅助验证）

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This book constitutes the refereed proceedings of the 13th International Conference on Computer Aided Verification, CAV 2001, held in Paris, France in July 2001.
The 33 revised full papers presented were carefully reviewed and selected from 106 regular paper submissions; also included are 13 reviewed tool presentations selected from 27 submissions. The book offers topical sections on model checking and theorem proving, automata techniques, verification core technology, BDD and decision trees, abstraction and refinement, combinations, infinite state systems, temporal logics and verification, microprocessor verification and cache coherence, SAT and applications, and timed automata.

Invited Talk
Software Documentation and the Verification Process
Model Checking and Theorem Proving
Certifying Model Checkers
Formalizing a JVML Verifier for Initialization in a Theorem Prover
Automated Inductive Verification of Parameterized Protocols
Automata Techniques
Efficient Modelk Chacking via Buchi Tableau Automata
Fast LTL to Buchi Automata Translation
A Practical Approach to Coverage in Model Checking
Verification Core Technology
A Fast Bisimulation Algorithm
Symmetry and Reduced Symmetery in Model Checking
Transformation-Based Verification Usding Generalized Retiming
BDD and Decision Procedures
Meta-BDDs:A Decomposed Representation for Layered Symbolic Manipulation of Boolean Functions
CLEVER:Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination
Finite Instantiations in Equivalence Logic with Uninterpreted Functions
Abstraction and Refinement
Model-Checking with Formula-Dependent Abstract Models
Verifying Network Protocol Implementations by Symbolic Refinement Checking
Automatic Abstraction for Verifcation of Timed Circuits and Systems
Combinations
Automated Verification of a Randomized Distributed Concensus Protocol Using Cadence SMV and PRISM
Analysis of Recursive State Machines
Parameterized Verification with Automatically Computed Inductive Assertions
Tool Presentations:Rewriting and Theorem-Proving techqiues
EVC:A Validity Checker for the Logic of Equality with Uniterpreted Functions and Memories Exploiting Positive Equality and Conservative Transformations
AGVI-Automatic Generation Verification and Implementation of Security PRotocols
ICS:Integrated Canonizer and Solver
……
Invited Talk
Infinite State Systems
Temporal Logics and Verification
Tool Presentations:Model-Checking and Automata Techniques
Microprocessor Verifcation Cache Coherence
SAT BDDs and Applications
Timed Automata
Author Index